View LC750512E_4180220.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : ENA0179
LC750512E
Overview
CMOS IC
Audistry support Audio DSP
The LC750512E is a single-chip audio DSP equipped with an Audio interface unit with features such as audio algorithm and lip-sync functions, which are required by audio/video-related products for which higher and higher sound quality levels are being demanded. The microcontroller has a CCB (Computer Control Bus) and I2C (Inter-Integrated Circuit) -support interface.
Features
1. Hardware configuration that allows installation of audio algorithm functions related to audio/video products * Program ROM: 24 bitsx8K words * Data RAM: 24 bitsx4K wordsx2 planes, 24 bitsx1K wordsx2 planes * Audio interface: I2S input, MSB first right justified, MSB first left justified (1 port) * Audio interface: I2S output, MSB first right justified, MSB first left justified (3 ports) * Analog input: 1 port (2 channel stereo), Analog output: 1 port (2 channel stereo) 2. Audio algorithms for audio/video-related products installed * Lip sync function (correcting time lags up to 80ms between audio and video at a 48kHz sampling frequency) * Audistry function (Mono-to-Stereo Creator, Suound Space Expander, Sound Space for Headphones, Intelligent Volume Control, Natural bass) * Equalizer function (3 bands/channel, common to L and R channels) * Volume control function (0 to -79dB, in 1dB increments, -) * Bass/treble control (18 dB in 1dB increments) and other basic control functions * Audistry mode/S3S mode user selectable, enabling SANYO's proprietary surround mode Audistry mode
Effect Audistry Algorithm (Name) Mono-to-Stereo Creator Sound Space Expander Sound Space for Headphones Intelligent Volume Control Natural Bass Remarks Generates a pseudo stereo sound from a mono signal Creates pseudo sound field (speaker) Creates pseudo sound field (headphone) AGC processing Low frequency enhancement
* Audistry and the sound shell logo are trademarks of Dolby Laboratories. Dolby is a registered trademark of Dolby Laboratories, Inc.
Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.
83006 / 61506HKIM No.A0179-1/9
LC750512E
S3S mode
Effect Low frequency enhancement Surround S-Live Digital AViSS Algorithm (Name) Remarks SANYO's proprietary low frequency enhancement algorithm SANYO's proprietary sound field control algorithm
The audio processing functions listed in the table below can be installed by making changes to the program ROM. (These functions have not been installed in the LC750512E).
Effect Surround Low frequency enhancement Sound field correction Virtual surround Low- and high-frequency enhancement Low- and high-frequency augumentation Algorithm (Name) Dolby Prologic II TruBass Focus SRS 3D,TruSurround Dedekind BBE Remarks Registered trademark of Dolby Laboratories, Inc. Registered trademark of SRS Labs, Inc. Registered trademark of SRS Labs, Inc. Registered trademark of SRS Labs, Inc. Registered trademark of Dedekind R&D Registered trademark of BBE Sound Inc.
Note 1: Users must be licensees of the algorithms listed. Model names are subject to change. Note 2: Processing estimates for using the algorithms will be based on the combinations in which the desired functions are used. 3. Microcontroller interface * CCB and I2C support 4. Supply voltages * Analog: 3.3V, 5V * Digital: 1.8V, 3.3V
Specifications
Absolute Maximum Ratings at VSS = 0V, AVSS = 0V
Ratings Parameter Supply voltage (A/D, D/A, volume, etc.) Supply voltage (A/D, D/A, volume, etc.) Supply voltage (crystal oscillator) Supply voltage (I/O interface block ) Supply voltage (DSP core block, PLL block) Maximum input voltage (A/D, D/A, volume, etc.) Maximum input voltage (DSP core block) (I/O interface block) VIN2 VIN1 VDD max4 DVDD1, DVDD2, DVDD3, DVDD4 PLLDVDD, PLLAVDD, PLLPWRR INL, INR EVRINL, EVRINR TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 SCKI, LRCKI, BCKI, DATAI, CE, SCL/CL, I2CBUSY/DI, SDA/DO, MCUIFSEL, XPDESC, RSTB, PWDB, INTB, XSEL0, XSEL1, XSEL2 Maximum output voltage Allowable power dissipation Maximum output current Operating temperature Storage temperature VOUT Pd max IO Topr Tstg CVDD Conditions: audio disabled operating state, mounted on a standard board* SDA/DO 0 -20 -55 -0.3 CVDD+0.3 850 4 +75 +125 V mW mA C C -0.3 CVDD+0.3 (max+3.96V) V VDD max2 VDD max3 XVDD CVDD1, CVDD2, CVDD3, CVDD4 VDD max1 BVDD1 Symbol VDD max1 Conditions AVDD1, AVDD2, AVDD3 min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 typ max +6.0 +3.96 +3.96 +3.96 +2.16 AVDD+0.3 (max+6.0V) unit
V V V V V V
*: Standard board: 76.1mmx114.3mmx1.6mm; glass epoxy resin
No.A0179-2/9
LC750512E
Allowable Operating Ranges at Ta = -20 to +75C, VSS = 0V, AVSS = 0V
Ratings Parameter Supply voltage (analog block) Supply voltage (analog block) Supply voltage (crystal oscillator) Supply voltage (digital block) Supply voltage (digital block, PLL) High-level input voltage Symbol AVDD BVDD XVDD CVDD DVDD VIH_D Conditions AVDD1, AVDD2, AVDD3 BVDD1 XVDD CVDD1, CVDD2, DVDD3, DVDD4 DVDD1, DVDD2, DVDD3, DVDD4 PLLDVDD, PLLAVDD, PLLPWRR TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 SCKI, LRCKI, BCKI, DATAI, CE, SCL/CL, I2CBUSY/DI, SDA/DO, MCUIFSEL, XPDESC, RSTB, PWDB, INTB, XSEL0, XSEL1, XSEL2 Low-level input voltage VIL_D TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 SCKI, LRCKI, BCKI, DATAI, CE, SCL/CL, I2CBUSY/DI, SDA/DO, MCUIFSEL, XPDESC, RSTB, PWDB, INTB, XSEL0, XSEL1, XSEL2 Crystal oscillator frequency Fop XIN, XOUT 18.432 MHz VSS 0.2xCVDD V 0.8xCVDD CVDD V min +4.75 +3.0 +3.0 +3.0 +1.62 typ max +5.25 +3.6 +3.6 +3.6 +1.98 unit V V V V V
Electrical Characteristics for the Allowable Operating Ranges
Ratings Parameter High-level input current Symbol IIH Pin name TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 SCKI, LRCKI, BCKI, DATAI, CE, SCL/CL, I2CBUSY/DI, SDA/DO, MCUIFSEL, XPDESC, RSTB, PWDB, INTB, XSEL0, XSEL1, XSEL2 Low-level input current IIL TEST0, TEST1, TEST2, TEST3, TEST4, TEST5, TEST6, TEST7 SCKI, LRCKI, BCKI, DATAI, CE, SCL/CL, I2CBUSY/DI, SDA/DO, MCUIFSEL, XPDESC, RSTB, PWDB, INTB, XSEL0, XSEL1, XSEL2 High-level output voltage VOH(1) TEST6, TEST7, LRCKO, BCKO, DATAO0, DATAO1, DATAO2, I2CBUSY/DI, EMPF, GPFLAG, MRREQ, XSEL0, XSEL1, XSEL2 VOH(2) SCKO, SDA/DO IOH=-4mA CVDD-0.4 CVDD-0.4 V IOH=-2mA -5 A VIN2=VIN3=0V 5 A Conditions VIN2=VIN3=CVDD min typ max unit
Continued on next page.
No.A0179-3/9
LC750512E
Continued from preceding page.
Ratings Parameter Low-level output voltage Symbol VOL(1) Pin name TEST6, TEST7, LRCKO, BCKO, DATAO0, DATAO1, DATAO2, I2CBUSY/DI, SDA/DO EMPF, GPFLAG, MRREQ, XSEL0, XSEL1, XSEL2 VOH(2) Output off leakage current IOFF(1) SCKO, SDA/DO XSEL0, XSEL1, XSEL2, TEST6, I2CBUSY/DI, SCKO, SDA/DO IOFF(2) XSEL0, XSEL1, XSEL2, TEST6, I CBUSY/DI, SCKO, SDA/DO Full scale input level Analog output level Reference voltage output Current drain VIN VOUT Vref I_XVDD INL, INR AOUT1, AOUT2 VREF1, VREF2 XVDD Conditions: audio disabled operating state, mounted on a standard board* XVDD=3.3V I_AVDD AVDD1, AVDD2, AVDD3 Conditions: audio disabled operating state, mounted on a standard board* AVDD=5V, I_BVDD BVDD1 Conditions: audio disabled operating state, mounted on a standard board* BVDD=3.3V I_CVDD CVDD1, CVDD2, CVDD3, CVDD4 Conditions: audio disabled operating state, mounted on a standard board* CVDD=3.3V I_DVDD DVDD1, DVDD2, DVDD3, DVDD4 PLLDVDD, PLLAVDD, PLLPWRR Conditions: audio disabled operating state, mounted on a standard board* DVDD=1.8V 65 85 1.8 2.4 2 3.5 mA 50 65 1.2 1.6 2.35 2.5 0.4xAVDD (max2Vp-p) 0.6xAVDD (max3Vp-p) 2.65 Vp-p Vp-p V
2
Conditions IOH=2mA
min
typ
max
unit
0.4
V
IOH=4mA VOUT=CVDD
0.4 5
VOUT=0V -5
A
*: Standard board: 76.1mmx114.3mmx1.6mm; glass epoxy resin
No.A0179-4/9
LC750512E
Analog Characteristics Conditions: AVDD = 5V, BVDD = CVDD = 3.3V, DVDD = 1.8V, fs = 48kHz, audio signal frequency = 1kHz Frequency bandwidth measured from A/D input to volume output: 10Hz to 20kHz, with a SANYO DSP evaluation board used Test circuit configured with circuits externally attached to LC750512E; tested with signals passed straight through the DSP at room temperature using an audio analyzer (System 2) as the test device
Parameter S/N Dynamic range THD+N Ratings min 80 80 typ 90 90 -75 -70 max unit dB dB dB Conditions A-weighted, input conditions: 2Vp-p A-weighted Input conditions: 1.5Vp-p, See Note.
Note: THD+N denotes the characteristics at which the input (1.5Vp-p) reduced by 3dB from the full-scale input is optimum. Conditions: AVDD = 5V, BVDD = CVDD = 3.3V, DVDD = 1.8V, fs = 48kHz, audio signal frequency = 1kHz Frequency bandwidth measured from digital input to volume output: 10Hz to 20kHz, SANYO DSP evaluation board used Test circuit configured with circuits externally attached to LC750512E; tested with signals passed straight through the DSP at room temperature using an audio analyzer (System2) as the test device
Parameter S/N Dynamic range THD+N Ratings min 83 83 typ 93 93 -75 -70 max unit dB dB dB Conditions A-weighted, input conditions: 0dBFS A-weighted Input conditions: -3dBFS, See Note.
Note: THD+N denotes the characteristics at which the input reduced by 3dB from the full-scale input is optimum.
Package Dimensions
unit : mm 3255
17.2 60 61 41 40
0.8
14.0
80 1 (0.83)
3.0max (2.7)
21 0.65 0.25 20 0.15
0.1
SANYO : QFP80(14X14)
14.0 17.2
No.A0179-5/9
LC750512E
Pin Assignment
DAOUTR DAOUTL EVRINR EVRINL AOUT2 AOUT1 AVDD1 AVDD2 AVDD3 25 AVDD4 24 AVSS4 BVDD1 BVSS1 23 22 21 20 19 18 17 16 15 14 13 12 AVSS1 INR AVSS2 VREF1 VREF2 AVSS3 26
38
37
INL
32
31
30
29
28
40
39
36
35
34
TEST6 XSEL0 XSEL1 XSEL2 CVSS1 CVDD1 LRCKI BCKI DATAI SCKI DVSS1 DVDD1 SCKO TEST7 DATAO2 DATAO1 DATAO0 BCKO LRCKO CVSS2
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 SDA/DO MRREQ GPFLAG MCUIFSEL XPDESC CVDD2 DVSS2 DVDD2 DVSS3 SCL/CL DVDD3 EMPF PDEN I2CBUSY/DI PWDB RSTB INTB CE
33
27
TEST5 TEST4 TEST1 TEST0 CVSS4 CVDD4 XVDD XIN XOUT XVSS DVDD4 DVSS4 TEST3 TEST2 PLLDVSS PLLDVDD PLLAVSS PLLAVDD PLLGNDR PLLPWRR
LC750512E
11 10 9 8 7 6 5 4 3 2 1 CVSS3 CVDD3 79 80
Top view
Pin Functions
Pin Name INL INR DAOUTL DAOUTR EVRINL EVRINR AOUT1 AOUT2 LRCKI BCKI DATAI LRCKO BCKO DATAO0 DATAO1 DATAO2 SCKI SCKO RSTB PWDB Input/Output AI AI AO AO AI AI AO AO I I I O O O O O I I/O I I Lch ADC analog input Rch ADC analog input Lch DAC analog output Rch DAC analog output Lch EVR input Rch EVR input Lch EVR output Rch EVR output LR clock input Bit clock input Data input LR clock output Bit clock output Data output 0 Data output 1 Data output 2 External clock input DAC master clock output Reset input (low active) Power down input (low active) Function Pin No. 37 38 29 30 28 31 27 32 47 48 49 59 58 57 56 55 50 53 67 66
Continued on next page.
No.A0179-6/9
LC750512E
Continued from preceding page.
Pin Name INTB MCUIFSEL CE SCL/CL I CBUSY/DI SDA/DO EMPF GPFLAG MRREQ XPDESC PDEN XSEL0 XSEL1 XSEL2 TEST7 TEST0, TEST1, TEST2, TEST3, TEST4, TEST5 TEST6 XIN XOUT XVDD XVSS VREF1 VREF2 AVDD1 AVSS1 AVDD2 AVSS2 AVDD3 AVSS3 AVDD4 AVSS4 BVDD1 BVSS1 CVDD1, CVDD2, CVDD3, CVDD4 CVSS1, CVSS2, CVSS3, CVSS4 DVDD1, DVDD2, DVDD3, DVDD4 DVSS1, DVSS2, DVSS3, DVSS4 PLLPWRR PLLGNDR PLLAVDD PLLAVSS PLLDVDD PLLDVSS Powering for PLL (ESD) (1.8V) GND for PLL (ESD) Power supply for PLL (1.8V) GND for PLL Digital power supply for PLL (1.8V) Digital GND for PLL 1 2 3 4 5 6 Digital GND 51, 64, 74, 9 Digital power supply (1.8V) 52, 65, 75, 10 Digital GND 45, 60, 79, 16 AO AO I/O Test pin Crystal oscillator input Crystal oscillator output Power supply for crystal oscillator GND for crystal oscillator Reference voltage output pin 1 (ADC) Reference voltage output pin 2 (DAC, EVR) ADC analog power supply (+5V) ADC analog GND VREF VDD (+5V) VREF GND EVR analog VDD (+5V) EVR analog GND DAC analog VDD (+5V) DAC analog GND Analog chip logic power supply (+3.3V) Analog chip logic GND Digital power supply (3.3V) 41 13 12 14 11 36 35 40 39 34 33 25 26 24 23 22 21 46, 61, 80, 15
2
Input/Output I I I I I/O I/O O O O I O I/O I/O I/O I I Interrupt input (low active)
Function
2
Pin No. 68 69 70 71
Microcontroller interface select input (CCB: low, I C: high) Microcontroller interface chip enable, fixed at high when I2C is selected. Microcontroller interface clock input Microcontroller interface data input/I C BUSY output Microcontroller interface data input/output CCB input register status monitor flag DSP-to-MCU general-purpose flag (high active) DSP-to-MCU communication error flag DSP power down reset signal (low active) DSP power down signal (high active) Crystal frequency select signal 0 Crystal frequency select signal 1 Crystal frequency select signal 2 Test pin Test pin
2
72 73 78 77 76 62 63 42 43 44 54 17, 18, 7, 8, 19, 20
No.A0179-7/9
LC750512E
Block Diagram
DAOUTL (C 1F) INR ADC (20 bits) DSP/CORE (24 bits) DAC (20 bits) R L.P.F. AOUT1 Vref DAOUTR (C 1F) R INL ADC (20 bits) DAC (20 bits) L.P.F. AOUT2 Vref Audio I/F Program ROM Audio I/F Audio I/F Audio I/F DATAO2 PLLAVDD 1.8V PLLAVSS Data RAM PLLDVDD 1.8V PLLDVSS AVDD1-4 5V AVSS1-4 Delay RAM BVDD1 BVSS1 3.3V LRCKO BCKO DATAO0 EVRINR EVRINL
LRCKI BCKI DATAI
DATAO1
CVDD1-4 3.3V CVSS1-4 DVDD1-4 1.8V DVSS1-4 PLLPWPR PLLGNDR XSEL0, 1, 2 VREF1 VREF2 XOUT PDEN XPDESC CE SCL/CL 2 I CBUSY/DI SDA/DO MCUIFSEL TEST7,5-0 TEST6 GPFLAG MRREQ PWDB EMPF SCKI SCKO RSTB INTB XIN PLL VCO CCB or I C
2
XVDD XVSS
3.3V
For sample external circuit configurations, see "LC750512E External Circuit Configuration Examples (Draft)."
No.A0179-8/9
LC750512E
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of June, 2006. Specifications and information herein are subject to change without notice.
PS No.A0179-9/9

▲Up To Search▲

Price & Availability of LC750512E

	To Download LC750512E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .